Vinyl ADC · Assembly bench

One wire at a time.

Use this visual guide with WaveForms, your BNC adapter, two probes and the W1 coax. Select a wire, match the board orientation, then use the enlarged pad view to connect it.

Current route: manual WaveFormsKorad = +5 V onlyChannels stay disconnected

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Set up first: BNC jumpers DC · probes 10× · W1 output 0 Ω

1Scope 1 BNCProbe 1 → tip + ground clip

2Scope 2 BNCProbe 2 → tip + ground clip

W1Wavegen W1 BNCCoax → centre signal + shield GND

V+Remaining red V+ wireDigital board’s +3.3 V only

Find the adapter’s printed connector labels; this overview does not depict its physical port order. Set both scope coupling jumpers to DC on the adapter—the default may be AC. Set the W1 output-impedance jumper to 0 Ω; do not add a 50 Ω terminator. Set both probes to 10× and both WaveForms scope channels’ attenuation to 10×. All voltages below are the corrected values at the probe tip. Compensate the probes in the first visual step.

Probe ground clips and BNC shields are common ground. A negative rail is measured with the tip, never the ground clip. The BNC adapter makes the scope inputs single-ended. Leave unused scope flywires, W2, V− and DIO outputs disconnected/off.

Coax board end: use a BNC-to-clips or BNC-to-terminal breakout. The centre conductor is W1 signal; the outer shield is GND. If your cable has a BNC connector at both ends, it cannot attach directly to PCB header pins without a suitable breakout. Do not push a bare BNC centre pin onto a PCB pad.

Before the board steps, complete the unpowered assembly inspection. Check pin 1 and component positions in KiCad against your actual board; the illustrations use the current PCB files. Use grabbers on component leads or properly soldered insulated test tails for crowded IC pads. Do not balance loose probe tips across neighbouring pins.

Reference: Digilent BNC adapter setup and scope probe attenuation. The graphical route is manual only: the existing SDK assumes direct 1× flywire inputs and must not be used with these 10× probes without a driver change.

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Power measurements — limits for the graphical BNC fixture

Keep the wiring shown in the selected visual step. With both probe switches and WaveForms attenuation at 10×, displayed voltages refer to the probe tip. Use DC coupling jumpers. Ground clips stay on GND.

Measurement	Initial screening range
+5 V	4.75–5.25 V
Generated negative rail	−5.25 to −3.50 V
VREF_P / VREF_N	+2.35…+2.65 V / −2.65…−2.35 V
Reference tracking	Within 3% of ±half the measured +5 V
Gross ripple	≤150 mVpp; capture at least 8 ms at ≥1 MS/s, with the complete DC rail visible

These are provisional fault screens, not a measurement of microvolt noise. Record current and voltages. The negative supply is generated by the charge pump, not regulated to precisely −5 V. If it is missing, verify the pump clock and diode/capacitor polarity. Positive voltage on the negative rail, persistent CC or heating: turn off and inspect. No channel load is permitted until decoupling is fitted.

Digital measurements — limits for the graphical BNC fixture

Keep the visual fixture: J1 2–3, external clock on J2.7, both probes at 10× with matching software scaling, DC coupling. Power off for every clock-pair or mux-case change.

Measurement	Initial screening range
Supplies	+5 V: 4.75–5.25 V; +3.3 V: 3.15–3.45 V
5 V logic	Low −0.3…0.45 V; high 4.0…5.3 V
Pi-facing 3.3 V logic	Low −0.3…0.45 V; high 2.7…3.6 V
Clocks	±2% of the selected nominal frequency, 35–65% duty cycle
Divider relationships	BCLK = CLK6M ÷2; MCLK = ÷4; PUMP = ÷32; LRCLK = ÷128

MCLK low selects QR; high selects QL. Test QL/QR = 0/0, 1/0, 0/1 and 1/1 for both raw DIN and PI_DIN. Ignore switching edges when comparing settled levels. All channel boards remain disconnected during the rail-tie tests. Pi clocks should retain the raw clock polarity, with a short propagation delay; 50 MS/s gives 20 ns per sample, not precision jitter measurement.

Reference notes, limits and troubleshooting — older flywire fixtures

For your BNC equipment, follow the graphical route above. These detailed notes also describe the original direct-flywire fixture. References to scope 1−/2− mean ground clips in the BNC setup, and the old SDK scripts assume 1× direct inputs. Do not switch to a second fixture halfway through a test.

1 · Where does −5 V come from?

The KD3005D has one adjustable output. At 5.00 V, the red terminal is 5 V above the black terminal. It cannot provide independent +5 V and −5 V rails around the same ground simultaneously. The green terminal is protective earth, not a third supply output; leave it unused for this fixture and do not alter any existing earth bonds.

Your power board uses U1 (74HC244), C4, D1/D2, C5/C6 and R1 as an inverting charge pump and filter. With +5 V and a 192 kHz, 0–5 V input at PUMP, it generates a negative voltage at power J3 pin 16. The net is called “−5V”, but it is not regulated to exactly −5.000 V. Its voltage depends on load and losses. No pump clock means no useful negative supply.

Disconnect the Korad leads from every PCB. Power the supply on and set 5.00 V and a 0.100 A / 100 mA current limit using its voltage/current adjustment controls. Check the displayed setpoints; the current setting is a limit, not a current forced into the board.
Switch the Korad POWER off before attaching leads. On the KD3005D, do not assume a separate output-enable button exists. Whenever this guide says “bench off”, use POWER off if that is your available control. Let the output discharge and verify near 0 V before handling the board.
For the standalone power test, red goes to power J3.2 (+5V); black goes to power J3.1 (GND). AD3 GND and both scope minus leads join this same GND.
When instructed to power on, watch the supply. Normal operation should settle in CV. Persistent CC, an OCP trip, unexpected current or heating means switch off and investigate. Do not raise the limit just to make a failed test continue.

Measure a negative rail with scope 2+ on the negative rail and 2− on GND. A multimeter uses red on the negative rail, black on GND and should display a minus sign. Never put AD3 GND on the negative rail.

100 mA is a provisional protection setting for a standalone power or digital board, not a measured consumption specification. Use 100 mA initially for the unloaded power + digital pair too. Current-limit trips require diagnosis.

2 · Unpowered inspection and finding pins on bare copper

Keep both channel boards unplugged. Remove all external power, USB power paths and signal sources from the boards. Use an insulated work surface.
Open the matching PCB in KiCad. Hover a pad to read its reference, pin number and net; match it against the PCB map below. “J3.2” means connector J3, pin 2, not the second pad from whichever side you are looking at. The underside view is mirrored. The power bus is J3; digital is J4; channels are J7.
Check IC notch/pin-1 orientation, solder bridges, copper whiskers and every required wire link. On bottom-only power copper, fit WL1A–WL1B. On bottom-only digital copper, fit all nine WL pairs and the extra U8.3-to-BCLK-anchor and U8.11-to-DIN-anchor connections shown in the assembly guide. Inspect the tight clearances around digital C11.
Power-board polarity: C5 and C6 positive leads go to GND; their negative leads face the negative supply nodes. C4 positive faces the U1 driver output. D1’s cathode band faces GND; D2’s cathode band faces the C4/D1 pump junction. Verify against KiCad, not package position alone.
With a multimeter, check continuity of intended links and GND connections, and check each supply against GND for an unintended short. Capacitors may cause a brief beep or a resistance that rises; a persistent near-zero reading requires investigation. Do not use resistance/continuity mode on a powered board.
Confirm digital U3 is 74HCT132, not 74HC132; the 3.3 V external clock relies on HCT input thresholds. Confirm the digital board’s own five 100 nF capacitors are fitted. X1 can remain empty.

All grounds on the 2×8 bus are odd-numbered pins. Even pins: 2 +5V · 4 VREF_P · 6 VREF_N · 8 MCLK · 10 PUMP · 12 QL · 14 QR · 16 −5V. Verify orientation in KiCad before making any connection.

3 · Power board alone — generate and measure the negative rail

Choose either the terminal script or manual WaveForms for this test. They cannot own the AD3 at the same time. Leave W2, V+, V− and digital pattern outputs off and disconnected.

Option A: guided SDK test with saved captures

Close WaveForms. In a terminal, run:

cd /home/mads/Projects/vinyl-adc
python assembly/bench/run.py devices
python assembly/bench/run.py power

The script first checks W1 with no PCB attached, then prompts for the power-board wiring and two sets of rail measurements. Type READY, ON and OFF only after completing the requested action. It cannot switch your Korad off. Reports and raw captures appear under assembly/bench/results/; use “Board tests · AD3” below to refresh results. Multiple devices: add --serial YOUR_SERIAL.

Option B: manual WaveForms test

Open WaveForms with no test script running. In Wavegen → W1, select Square, 192 kHz, 50% symmetry, amplitude 2.5 V, offset +2.5 V. That means 5 Vpp, 0–5 V, not ±5 V. Keep it stopped while wiring.
With the PCB disconnected, connect scope 1+ to W1, 1− to AD3 GND. Set DC coupling/direct 1× flywires, about 1 V/div and 2 µs/div; trigger on channel 1 rising at about 2.5 V. Run W1 and Scope. Confirm approximately 192 kHz, 0 V low and 5 V high, with no substantial overshoot. Stop W1.
Switch the Korad off, then connect the fixture in the table below. Scope 1 now measures +5 V; scope 2 measures the negative rail. Set both scope channels DC coupled, about 1 V/div, with offsets that show their respective rails. Use Auto trigger.
Turn the Korad on at 5.00 V / 100 mA. If it settles in CV, start W1 immediately. Do not leave the pump input floating while the board is powered. Wait about one second, then record +5 V, the negative rail and supply current. Stop if a rail is positive where it should be negative.
For ripple, capture at least 8 ms at ≥1 MS/s, with the DC rail visible. Use peak-to-peak measurements. The provisional screen is ≤150 mVpp; this detects large faults, not microvolt noise performance.
Turn the Korad off, stop W1, wait for discharge, and move only scope 1+ to J3.4 and scope 2+ to J3.6. Keep both minus leads on GND. Repeat the power-on sequence and measure the references.
Finish by switching the Korad off, stopping all AD3 outputs and checking that rails have discharged before disconnecting.

Standalone power fixture — power board J3
Lead	Connect to	Purpose
Korad red; scope 1+	J3.2 · +5V	Only external board supply
Korad black; AD3 GND; scope 1− and 2−	J3.1 · GND	Common reference
AD3 W1	J3.10 · PUMP	192 kHz, 0–5 V
Scope 2+	J3.16 · −5V	Generated negative rail, never an AD3 supply connection
Scope 1+ in reference step	J3.4 · VREF_P	Positive reference
Scope 2+ in reference step	J3.6 · VREF_N	Negative reference

Provisional power-board screening limits
Measurement	Accept for initial screening
+5 V	4.75–5.25 V
Negative rail	−5.25 to −3.50 V; observe the minus sign
VREF_P	+2.35 to +2.65 V
VREF_N	−2.65 to −2.35 V
Reference accuracy	Each reference within 3% of ±½ the measured +5 V
Gross ripple	≤150 mVpp on each rail/reference

Passing unloaded measurements does not establish the pump’s current capacity for both channels. That is checked later under the actual load.

4 · Digital board alone — AD3 replaces the missing oscillator

Use manual WaveForms for this external-clock procedure. The existing digital, left and right SDK tests expect the installed oscillator and can reset W1. Do not run them with this fixture. Keep the power board, channels and Pi disconnected.

With all power off, move J1 to 2–3 to select GPCLK0. Leave X1 empty. Tie QL (J4.12) and QR (J4.14) to board GND to prevent floating mux inputs.
Before attaching the board, check AD3 V+ set to +3.30 V with the scope or multimeter; then disable it. V− remains off. The Korad supplies +5 V; AD3 V+ supplies the separate +3.3 V rail. Do not connect V+ to +5 V or to another 3.3 V supply.
Change W1 to Square, 6.144 MHz, 50% symmetry, amplitude 1.65 V, offset +1.65 V (3.3 Vpp, nominal 0–3.3 V). With no PCB attached, measure W1 using scope 1+ and a short ground return; use roughly 50 ns/div and 500 mV/div, with the waveform centred on screen. Run the scope at ≥50 MS/s.
Verify frequency and input swing: low below 0.8 V, high above 2.0 V, and the waveform staying approximately within 0–3.3 V (screen −0.3 to +3.8 V). Rounded edges are expected over flywires; confirm clean threshold crossings and the downstream clock at U4.10. Do not increase amplitude to compensate blindly. Stop W1 before connecting it to J2.7.
Wire the table below. Make sure all Pattern Generator / Static I/O outputs are disabled; DIO pins are observation inputs only. Connect the scope to +5 V and +3.3 V for the first rail check.
Enable AD3 V+ at 3.30 V, turn the Korad on at 5.00 V / 100 mA, and start W1 immediately once CV is established. Verify +5 V is 4.75–5.25 V and +3.3 V is 3.15–3.45 V. Record the +5 V current. Stop for persistent CC, heating or abnormal rails.
For each new probe location: Korad off → W1 stop → V+ off → wait for discharge → rewire. Restart V+, Korad, then W1. Capture the clocks below with the Logic instrument at ≥50 MS/s, about 200 µs total. Use an automatic capture initially so a missing clock does not just look like a trigger timeout.

Digital external-clock fixture — digital board J2
Lead	Connect to	Setting
Korad red	J2.1 · +5V	5.00 V / 100 mA initial limit
Korad black; AD3 GND; scope 1− and 2−	J2.2 · GND	Common reference
AD3 V+	J2.3 · +3V3	+3.30 V; V− off
AD3 W1	J2.7 · GPCLK0	6.144 MHz, nominal 0–3.3 V; J1 2–3

Clock observations — all listed DIO pins remain inputs
AD3 lead	Digital test point	Expected
DIO0	U4.10 · CLK6M	6.144 MHz, 5 V logic
DIO1	J4.8 · MCLK	1.536 MHz, 5 V logic
DIO2	U4.9 · BCLK	3.072 MHz, 5 V logic
DIO3	U4.4 · LRCLK	48 kHz, 5 V logic
DIO4	J2.4 · PI_BCLK	3.072 MHz, 3.3 V logic
DIO5	J2.5 · PI_LRCLK	48 kHz, 3.3 V logic
DIO10	J4.10 · PUMP	192 kHz, 5 V logic

Screen frequencies within ±2% and duty cycle within 35–65%. Also check that divider outputs track the measured CLK6M by ÷2, ÷4, ÷32 and ÷128 respectively. Use the scope to check voltage: 5 V logic low −0.3…0.45 V, high 4.0…5.3 V; Pi-facing logic low −0.3…0.45 V, high 2.7…3.6 V. A logic analyzer alone cannot establish safe output voltage.

Compare BCLK to PI_BCLK and LRCLK to PI_LRCLK with both scope channels: the paths should be non-inverting, with small propagation delay. At 50 MS/s, each sample is 20 ns; this is a gross polarity/timing check, not a precision jitter measurement.

5 · Digital data paths — test all four left/right combinations

Keep the standalone digital fixture and external clock. No channel boards may be attached while their Q bus inputs are tied to rails. Every tie change requires the full off/rewire/on sequence from step 4.

Keep DIO1 on MCLK. Add DIO6 and scope 1+ to U6.4 (DIN), DIO7 to J4.12 (QL), DIO8 to J4.14 (QR), and DIO9 plus scope 2+ to J2.6 (PI_DIN). Both scope minus leads remain at GND. Input 0 means tie to board GND; input 1 means tie to board +5 V. Do not drive these 5 V HC inputs from 3.3 V AD3 DIO outputs.

MCLK low selects QR; MCLK high selects QL
QL / QR ties	DIN and PI_DIN expected
0 / 0	Constant low
1 / 0	Follow MCLK
0 / 1	Inverse of MCLK
1 / 1	Constant high

Judge the centre of each MCLK half-cycle, after propagation delay. DIN is 5 V logic; PI_DIN must remain 3.3 V logic, using the voltage limits in step 4. Record actual QL/QR states as well as outputs. Save each capture with its case name. After finishing, power off and remove all four-case test ties before adding either channel.

6 · Power + digital — make the digital board drive the pump

Only continue after both standalone tests pass. Turn Korad and all AD3 outputs off and let the rails discharge. Remove the W1 wire from power J3.10. W1 will now drive digital J2.7 only.
Join the power J3 and digital J4 buses with the same numbered pins aligned, using the intended connectors. For a minimal flywire fixture, connect J4.1 to J3.1 (GND), J4.2 to J3.2 (+5V), and J4.10 to J3.10 (PUMP). Check continuity and absence of shorts while unpowered. No other bus wires are needed for this two-board pump test.
Use one Korad feed: red to digital J2.1, black to J2.2. Retain AD3 V+ to digital J2.3 at 3.30 V; W1 to J2.7 at 6.144 MHz / 0–3.3 V; J1 at 2–3. Leave the absent QL/QR inputs tied low during this two-board-only test.
Probe PUMP at power J3.10 with DIO10 and the negative rail at J3.16 with scope 2+. Scope 1+ measures J3.2. Start V+, Korad, then W1. Confirm 192 kHz reaches the power board and repeat the step 3 rail measurements, then references after powering off to move probes.
Record supply current and voltages. This establishes that the digital divider can operate the pump. It does not prove loaded channel performance. Shut down Korad, W1 and V+ before disconnecting.

There must be one driver on PUMP: AD3 W1 for the standalone power test, or the digital board for the combined test. Never connect both outputs to that net.

7 · Channel and complete-system tests — after the missing parts arrive

Do not power either channel with its seven 100 nF decoupling capacitors missing. You can finish visual inspection and unpowered continuity checks now. Check all 20 required top-side pad connections on each channel against its assembly map; unplated holes do not join top and bottom copper automatically.

The following automated route additionally requires the correct 6.144 MHz oscillator module installed at X1 and J1 set to 1–2. A two-lead passive crystal is not that module. With the capacitor shortage resolved but X1 still absent, finish steps 1–6 and stop here; these scripts do not yet maintain an external W1 clock during channel tests.

Fit the missing capacitors, inspect the channel soldering, and rerun digital screening with the installed oscillator. Close WaveForms before running SDK tests.
Test one channel at a time with the verified power and digital boards. Remove all QL/QR test ties before connecting a channel. Left J21 = 1–2; right J21 = 2–3. Follow the terminal fixture prompts. Start +5 V current limit at 0.20 A for power + digital + one channel; persistent CC remains a stop condition.
The scripts check loaded rails and references, grounded-input bit density, complementary feedback outputs and two 1 kHz signal levels: 0.10 and 0.25 V peak, zero offset. Keep the channel gain trimmer fixed. These are functional screens, not calibrated audio-quality measurements.
After each channel passes, power off and connect both channels with opposite J21 selections. Remove any remaining input ties. Recheck +5 V, negative rail, both references and supply current under full load before attempting capture. Do not assume the unloaded pump result proves sufficient current for the stereo stack.
Raspberry Pi capture and SNR/THD measurements are a later stage after electrical verification. No Pi connection is part of the procedures above.

# Only after the oscillator is installed and channel decoupling is complete:
python assembly/bench/run.py digital --ad3-3v3
python assembly/bench/run.py left --ad3-3v3
python assembly/bench/run.py right --ad3-3v3

Follow the full fixture instructions in the SDK test README and the per-board “Board tests · AD3” stage below. A simulated PASS does not qualify a physical board.

Troubleshooting and what to record

Observation	Next check, with power off before moving connections
Korad in CC; voltage collapses	Check shorts, IC orientation, reversed electrolytics, wrong bus alignment and a ground lead on −5V. Do not increase the current limit to bypass the symptom.
+5 V good, negative rail near 0 V	Verify 192 kHz at J3.10; then U1 supply and enables, WL1, pump capacitor/diode orientation and solder joints. No negative rail is expected with the clock stopped.
“−5V” is positive	Stop. Verify probe polarity and D1/D2 orientation against KiCad. Do not attach a channel.
Negative rail good, reference wrong	Check U2 orientation and supplies, reference resistor values and joints. Do not diagnose the negative reference until the negative rail is established.
No digital clocks	Check W1 running, J1 2–3, clock at J2.7, 74HCT132 fitted, +5 V, U4.10 clock and U4.11 reset held low. A floating or wrong clock-select connection can look like a dead counter.
All digital frequencies wrong by the same factor	Check W1 frequency and units. CLK6M is 6.144 MHz; the bus MCLK is 1.536 MHz.
5 V clocks good, Pi outputs missing	Check the separate +3.3 V rail, U8 and the required bottom-only-board wire links.
Mux wrong or erratic	Verify QL/QR are actually tied to the intended rails, U6 enable is low, MCLK reaches U6.1, and both channel boards are disconnected.
Clock stops when a script opens	Only one application owns the AD3. The normal digital/channel scripts assume X1 and can reset W1. Use the manual external-clock route above.
SDK cannot load or find AD3	Close WaveForms, inspect `python assembly/bench/run.py devices`, and check the installer notes. Device enumeration alone does not exercise hardware outputs.

For each run record: board/revision, date, clock source and measured frequency, Korad current limit and measured current, rail means and ripple, clock frequencies/levels, mux case results and any heating or failed checks. Save WaveForms captures and the workspace separately; the assembly backup does not include WaveForms files. Do not mark skipped tests as passed.

Stop sequence: Korad off → W1 stop → AD3 V+ off → verify discharge. If software freezes or USB disconnects, turn the Korad off yourself; software cannot guarantee shutdown after a lost connection.

Guide checked against the current PCB snapshot and existing provisional limits on 6 September 2026. No physical board measurements were made while writing it. References: KORAD KD-series manuals, KD-series manufacturer manual, RND-branded copy, AD3 electrical specifications, WaveForms Wavegen settings, local screening limits and validated probe plans.

PCB reference

Traces

Selected Top connection · square = pin 1
Coordinates in mm, KiCad absolute origin. Copper fills and exact pad shapes omitted; verify in KiCad.