◉ VINYL ADC ASSEMBLY BENCHRev D · PCBWay

START HERE · KORAD KD3005D + ANALOG DISCOVERY 3

One wire at a time.

Use this visual guide with WaveForms, your BNC adapter, two probes and the W1 coax. Select a wire, match the board orientation, then use the enlarged pad view to connect it.

Current route: manual WaveFormsKorad = +5 V onlyChannels stay disconnected

Loading today’s bench handoff…

Set up first: BNC jumpers DC · probes 10× · W1 output 0 Ω
1Scope 1 BNCProbe 1 → tip + ground clip
2Scope 2 BNCProbe 2 → tip + ground clip
W1Wavegen W1 BNCCoax → centre signal + shield GND
V+Remaining red V+ wireDigital board’s +3.3 V only

Find the adapter’s printed connector labels; this overview does not depict its physical port order. Set both scope coupling jumpers to DC on the adapter—the default may be AC. Set the W1 output-impedance jumper to 0 Ω; do not add a 50 Ω terminator. Set each WaveForms scope channel’s attenuation to match its physical probe: currently CH1 = 10×, CH2 = 1×. A reading wrong by 10× on one channel means that channel’s probe switch and software attenuation disagree. All voltages below are the corrected values at the probe tip. Compensate the probes in the first visual step.

Probe ground clips and BNC shields are common ground. A negative rail is measured with the tip, never the ground clip. The BNC adapter makes the scope inputs single-ended. Leave unused scope flywires, W2, V− and DIO outputs disconnected/off.

Coax board end: use a BNC-to-clips or BNC-to-terminal breakout. The centre conductor is W1 signal; the outer shield is GND. If your cable has a BNC connector at both ends, it cannot attach directly to PCB header pins without a suitable breakout. Do not push a bare BNC centre pin onto a PCB pad.

Before the board steps, complete the unpowered assembly inspection. Check pin 1 and component positions in KiCad against your actual board; the illustrations use the current PCB files. Use grabbers on component leads or properly soldered insulated test tails for crowded IC pads. Do not balance loose probe tips across neighbouring pins.

Reference: Digilent BNC adapter setup and scope probe attenuation. The graphical route is manual only: the existing SDK assumes direct 1× flywire inputs and must not be used with these 10× probes without a driver change.

Loading your PCB wiring diagrams…

Power measurements — limits for the graphical BNC fixture

Keep the wiring shown in the selected visual step. With each probe switch and its WaveForms channel attenuation in agreement (CH1 10×, CH2 1×), displayed voltages refer to the probe tip. Use DC coupling jumpers. Ground clips stay on GND.

MeasurementInitial screening range
+5 V4.75–5.25 V
Generated negative rail−5.25 to −3.50 V
VREF_P / VREF_N+2.35…+2.65 V / −2.65…−2.35 V
Reference trackingWithin 3% of ±half the measured +5 V
Gross ripple≤150 mVpp; capture at least 8 ms at ≥1 MS/s, with the complete DC rail visible

These are provisional fault screens, not a measurement of microvolt noise. Record current and voltages. The negative supply is generated by the charge pump, not regulated to precisely −5 V. If it is missing, verify the pump clock and diode/capacitor polarity. Positive voltage on the negative rail, persistent CC or heating: turn off and inspect. No channel load is permitted until decoupling is fitted.

Digital measurements — limits for the graphical BNC fixture

Keep the visual fixture: J1 1–2 (on-board crystal), nothing on J2.7, W1 disconnected, each probe’s software scaling matching its switch (CH1 10×, CH2 1×), DC coupling. Power off for every clock-pair or mux-case change.

MeasurementInitial screening range
Supplies+5 V: 4.75–5.25 V; +3.3 V: 3.15–3.45 V
5 V logicLow −0.3…0.45 V; high 4.0…5.3 V
Pi-facing 3.3 V logicLow −0.3…0.45 V; high 2.7…3.6 V
Clocks±2% of the selected nominal frequency, 35–65% duty cycle
Divider relationshipsBCLK = CLK6M ÷2; MCLK = ÷4; PUMP = ÷32; LRCLK = ÷128

MCLK low selects QR; high selects QL. Test QL/QR = 0/0, 1/0, 0/1 and 1/1 for both raw DIN and PI_DIN. Ignore switching edges when comparing settled levels. All channel boards remain disconnected during the rail-tie tests. Pi clocks should retain the raw clock polarity, with a short propagation delay; 50 MS/s gives 20 ns per sample, not precision jitter measurement.

Reference notes, limits and troubleshooting — older flywire fixtures

With the rev B digital board (on-board crystal) the SDK scripts are the primary route again: run them with --probe 10,1 for the BNC adapter (CH1 10× probe, CH2 1× probe), or without it for direct 1× flywires. References to scope 1−/2− mean ground clips in the BNC setup. Do not switch fixtures or the --probe setting halfway through a test.

1 · Where does −5 V come from?

The KD3005D has one adjustable output. At 5.00 V, the red terminal is 5 V above the black terminal. It cannot provide independent +5 V and −5 V rails around the same ground simultaneously. The green terminal is protective earth, not a third supply output; leave it unused for this fixture and do not alter any existing earth bonds.

Your power board uses U1 (74HC244), C4, D1/D2, C5/C6 and R1 as an inverting charge pump and filter. With +5 V and a 192 kHz, 0–5 V input at PUMP, it generates a negative voltage at power J3 pin 16. The net is called “−5V”, but it is not regulated to exactly −5.000 V. Its voltage depends on load and losses. No pump clock means no useful negative supply.

  1. Disconnect the Korad leads from every PCB. Power the supply on and set 5.00 V and a 0.100 A / 100 mA current limit using its voltage/current adjustment controls. Check the displayed setpoints; the current setting is a limit, not a current forced into the board.
  2. Switch the Korad POWER off before attaching leads. On the KD3005D, do not assume a separate output-enable button exists. Whenever this guide says “bench off”, use POWER off if that is your available control. Let the output discharge and verify near 0 V before handling the board.
  3. For the standalone power test, red goes to power J3.2 (+5V); black goes to power J3.1 (GND). AD3 GND and both scope minus leads join this same GND.
  4. When instructed to power on, watch the supply. Normal operation should settle in CV. Persistent CC, an OCP trip, unexpected current or heating means switch off and investigate. Do not raise the limit just to make a failed test continue.

Measure a negative rail with scope 2+ on the negative rail and 2− on GND. A multimeter uses red on the negative rail, black on GND and should display a minus sign. Never put AD3 GND on the negative rail.

100 mA is a provisional protection setting for a standalone power or digital board, not a measured consumption specification. Use 100 mA initially for the unloaded power + digital pair too. Current-limit trips require diagnosis.

2 · Unpowered inspection and finding pins on bare copper
  1. Keep both channel boards unplugged. Remove all external power, USB power paths and signal sources from the boards. Use an insulated work surface.
  2. Open the matching PCB in KiCad. Hover a pad to read its reference, pin number and net; match it against the PCB map below. “J3.2” means connector J3, pin 2, not the second pad from whichever side you are looking at. The underside view is mirrored. The power bus is J3; digital is J4; channels are J7.
  3. Check IC notch/pin-1 orientation, solder bridges, copper whiskers and every required wire link. On bottom-only power copper, fit WL1A–WL1B. On the rev B digital board, fit every wire link in the assembly guide’s wire-links step (16 anchors across MCLK, CLK6M, DIN, +3V3, GND and PI_DIN) including the component-side socket joints at U4.10, U6.1, U6.4 and U8.11.
  4. Power-board polarity: C5 and C6 positive leads go to GND; their negative leads face the negative supply nodes. C4 positive faces the U1 driver output. D1’s cathode band faces GND; D2’s cathode band faces the C4/D1 pump junction. Verify against KiCad, not package position alone.
  5. With a multimeter, check continuity of intended links and GND connections, and check each supply against GND for an unintended short. Capacitors may cause a brief beep or a resistance that rises; a persistent near-zero reading requires investigation. Do not use resistance/continuity mode on a powered board.
  6. Confirm digital U3 is 74HCT132 and U9 is the unbuffered 74HCU04, not a 74HC04. Check the Pierce parts around it: Y1 6.144 MHz, C16/C17 27 pF, R10 1 M, R11 2k2. Confirm the five 100 nF capacitors and that J1 is fitted across pins 1–2; nothing connects to J2.7.

All grounds on the 2×8 bus are odd-numbered pins. Even pins: 2 +5V · 4 VREF_P · 6 VREF_N · 8 MCLK · 10 PUMP · 12 QL · 14 QR · 16 −5V. Verify orientation in KiCad before making any connection.

3 · Power board alone — generate and measure the negative rail

Choose either the terminal script or manual WaveForms for this test. They cannot own the AD3 at the same time. Leave W2, V+, V− and digital pattern outputs off and disconnected.

Option A: guided SDK test with saved captures

Close WaveForms. In a terminal, run:

cd /home/mads/Projects/vinyl-adc
python assembly/bench/run.py devices
python assembly/bench/run.py power

The script first checks W1 with no PCB attached, then prompts for the power-board wiring and two sets of rail measurements. Type READY, ON and OFF only after completing the requested action. It cannot switch your Korad off. Reports and raw captures appear under assembly/bench/results/; use “Board tests · AD3” below to refresh results. Multiple devices: add --serial YOUR_SERIAL.

Option B: manual WaveForms test

  1. Open WaveForms with no test script running. In Wavegen → W1, select Square, 192 kHz, 50% symmetry, amplitude 2.5 V, offset +2.5 V. That means 5 Vpp, 0–5 V, not ±5 V. Keep it stopped while wiring.
  2. With the PCB disconnected, connect scope 1+ to W1, 1− to AD3 GND. Set DC coupling/direct 1× flywires, about 1 V/div and 2 µs/div; trigger on channel 1 rising at about 2.5 V. Run W1 and Scope. Confirm approximately 192 kHz, 0 V low and 5 V high, with no substantial overshoot. Stop W1.
  3. Switch the Korad off, then connect the fixture in the table below. Scope 1 now measures +5 V; scope 2 measures the negative rail. Set both scope channels DC coupled, about 1 V/div, with offsets that show their respective rails. Use Auto trigger.
  4. Turn the Korad on at 5.00 V / 100 mA. If it settles in CV, start W1 immediately. Do not leave the pump input floating while the board is powered. Wait about one second, then record +5 V, the negative rail and supply current. Stop if a rail is positive where it should be negative.
  5. For ripple, capture at least 8 ms at ≥1 MS/s, with the DC rail visible. Use peak-to-peak measurements. The provisional screen is ≤150 mVpp; this detects large faults, not microvolt noise performance.
  6. Turn the Korad off, stop W1, wait for discharge, and move only scope 1+ to J3.4 and scope 2+ to J3.6. Keep both minus leads on GND. Repeat the power-on sequence and measure the references.
  7. Finish by switching the Korad off, stopping all AD3 outputs and checking that rails have discharged before disconnecting.
Standalone power fixture — power board J3
LeadConnect toPurpose
Korad red; scope 1+J3.2 · +5VOnly external board supply
Korad black; AD3 GND; scope 1− and 2−J3.1 · GNDCommon reference
AD3 W1J3.10 · PUMP192 kHz, 0–5 V
Scope 2+J3.16 · −5VGenerated negative rail, never an AD3 supply connection
Scope 1+ in reference stepJ3.4 · VREF_PPositive reference
Scope 2+ in reference stepJ3.6 · VREF_NNegative reference
Provisional power-board screening limits
MeasurementAccept for initial screening
+5 V4.75–5.25 V
Negative rail−5.25 to −3.50 V; observe the minus sign
VREF_P+2.35 to +2.65 V
VREF_N−2.65 to −2.35 V
Reference accuracyEach reference within 3% of ±½ the measured +5 V
Gross ripple≤150 mVpp on each rail/reference

Passing unloaded measurements does not establish the pump’s current capacity for both channels. That is checked later under the actual load.

4 · Digital board alone — rev B with the on-board crystal oscillator

The rev B digital board clocks itself. U9 (74HCU04) and Y1 form a 6.144 MHz Pierce oscillator whose output reaches J1 pin 1; the J1 shunt across pins 1–2 feeds it to the 74HCT132 buffer. W1 is not connected to the digital board for any test. Keep the power board, channels and Pi disconnected for the standalone test.

Option A: guided SDK test with saved captures

Easiest at the bench: start the local browser front end with python assembly/bench/gui.py and open http://127.0.0.1:8090. It shows each step’s wiring, one big READY / ON / OFF button and the current field, and can continue an earlier aborted run without repeating its passed steps. Or, in a terminal, close WaveForms and run one of these, depending on the scope fixture:

cd /home/mads/Projects/vinyl-adc
python assembly/bench/run.py digital --ad3-3v3 --probe 10,1   # BNC adapter: CH1 10x probe, CH2 1x probe
python assembly/bench/run.py digital --ad3-3v3                # direct 1x scope flywires

The script prompts for the rails wiring and then two probe checks on header pins only: PI_BCLK/PI_LRCLK at J2.4/J2.5 (3.3 V levels and frequencies, the Pi-safety check) and MCLK/PUMP at J4.8/J4.10 (5 V bus clocks). No DIO harness and no QL/QR ties. Omit --ad3-3v3 only if a separate regulated +3.3 V supply feeds J2.3.

Option B: manual WaveForms test

  1. Open WaveForms with no test script running. In Wavegen → W1, select Square, 192 kHz, 50% symmetry, amplitude 2.5 V, offset +2.5 V. That means 5 Vpp, 0–5 V, not ±5 V. Keep it stopped while wiring.
  2. With the PCB disconnected, connect scope 1+ to W1, 1− to AD3 GND. Set DC coupling/direct 1× flywires, about 1 V/div and 2 µs/div; trigger on channel 1 rising at about 2.5 V. Run W1 and Scope. Confirm approximately 192 kHz, 0 V low and 5 V high, with no substantial overshoot. Stop W1.
  3. Switch the Korad off, then connect the fixture in the table below. Scope 1 now measures +5 V; scope 2 measures the negative rail. Set both scope channels DC coupled, about 1 V/div, with offsets that show their respective rails. Use Auto trigger.
  4. Turn the Korad on at 5.00 V / 100 mA. If it settles in CV, start W1 immediately. Do not leave the pump input floating while the board is powered. Wait about one second, then record +5 V, the negative rail and supply current. Stop if a rail is positive where it should be negative.
  5. For ripple, capture at least 8 ms at ≥1 MS/s, with the DC rail visible. Use peak-to-peak measurements. The provisional screen is ≤150 mVpp; this detects large faults, not microvolt noise performance.
  6. Turn the Korad off, stop W1, wait for discharge, and move only scope 1+ to J3.4 and scope 2+ to J3.6. Keep both minus leads on GND. Repeat the power-on sequence and measure the references.
  7. Finish by switching the Korad off, stopping all AD3 outputs and checking that rails have discharged before disconnecting.
Standalone power fixture — power board J3
LeadConnect toPurpose
Korad red; scope 1+J3.2 · +5VOnly external board supply
Korad black; AD3 GND; scope 1− and 2−J3.1 · GNDCommon reference
AD3 W1J3.10 · PUMP192 kHz, 0–5 V
Scope 2+J3.16 · −5VGenerated negative rail, never an AD3 supply connection
Scope 1+ in reference stepJ3.4 · VREF_PPositive reference
Scope 2+ in reference stepJ3.6 · VREF_NNegative reference
Provisional power-board screening limits
MeasurementAccept for initial screening
+5 V4.75–5.25 V
Negative rail−5.25 to −3.50 V; observe the minus sign
VREF_P+2.35 to +2.65 V
VREF_N−2.65 to −2.35 V
Reference accuracyEach reference within 3% of ±½ the measured +5 V
Gross ripple≤150 mVpp on each rail/reference

Passing unloaded measurements does not establish the pump’s current capacity for both channels. That is checked later under the actual load.

4 · Digital board alone — rev B with the on-board crystal oscillator

The rev B digital board clocks itself. U9 (74HCU04) and Y1 form a 6.144 MHz Pierce oscillator whose output reaches J1 pin 1; the J1 shunt across pins 1–2 feeds it to the 74HCT132 buffer. W1 is not connected to the digital board for any test. Keep the power board, channels and Pi disconnected for the standalone test.

Option A: guided SDK test with saved captures

Easiest at the bench: start the local browser front end with python assembly/bench/gui.py and open http://127.0.0.1:8090. It shows each step’s wiring, one big READY / ON / OFF button and the current field, and can continue an earlier aborted run without repeating its passed steps. Or, in a terminal, close WaveForms and run one of these, depending on the scope fixture:

cd /home/mads/Projects/vinyl-adc
python assembly/bench/run.py digital --ad3-3v3 --probe 10,1   # BNC adapter: CH1 10x probe, CH2 1x probe
python assembly/bench/run.py digital --ad3-3v3                # direct 1x scope flywires

The script prompts for the rails wiring, the DIO clock wiring and the four QL/QR mux cases, and records frequencies, duty cycles, Pi-side levels, the non-inversion delay screen and the mux truth table. Omit --ad3-3v3 only if a separate regulated +3.3 V supply feeds J2.3. The DIO flywires stay available on the BNC adapter’s pass-through header.

Option B: manual WaveForms test

  1. With all power off, fit J1 across pins 1–2. Tie QL (J4.12) and QR (J4.14) to board GND to prevent floating mux inputs.
  2. Before attaching the board, check AD3 V+ set to +3.30 V with the scope or multimeter; then disable it. V− remains off. The Korad supplies +5 V; AD3 V+ supplies the separate +3.3 V rail. Do not connect V+ to +5 V or to another 3.3 V supply.
  3. Wire the table below. Make sure all Pattern Generator / Static I/O outputs are disabled; DIO pins are observation inputs only. Connect the scope to +5 V and +3.3 V for the first rail check.
  4. Enable AD3 V+ at 3.30 V, then turn the Korad on at 5.00 V / 100 mA. Verify +5 V is 4.75–5.25 V and +3.3 V is 3.15–3.45 V. Record the +5 V current. Stop for persistent CC, heating or abnormal rails.
  5. First clock check: scope 1+ on J1.1 (raw Pierce output) and scope 2+ on U4.10 (CLK6M after the buffer). Expect 6.144 MHz within ±0.01 % on both, 5 V logic. No oscillation, or oscillation far from 6.144 MHz, means the Pierce stage itself is wrong; do not continue to the divider until it runs.
  6. For each new probe location: Korad off → V+ off → wait for discharge → rewire. Restart V+, then the Korad. Capture the clocks below with the Logic instrument at ≥50 MS/s, about 200 µs total. Use an automatic capture initially so a missing clock does not just look like a trigger timeout.
Standalone digital fixture — digital board J2
LeadConnect toSetting
Korad redJ2.1 · +5V5.00 V / 100 mA initial limit
Korad black; AD3 GND; scope 1− and 2−J2.2 · GNDCommon reference
AD3 V+J2.3 · +3V3+3.30 V; V− off
J1 shuntJ1.1 → J1.2On-board crystal selected; J2.7 (GPCLK0) left open
Minimum clock checks — two probe tips, header pins only
CheckScope 1+Scope 2+Expected
Pi-side clocksJ2.4 · PI_BCLKJ2.5 · PI_LRCLK3.072 MHz and 48 kHz, 3.3 V logic (highs 2.7…3.6 V)
Bus clocksJ4.8 · MCLKJ4.10 · PUMP1.536 MHz and 192 kHz, 5 V logic
If nothing runsJ1.1 · Pierce outputU4.10 · CLK6M6.144 MHz on both; see troubleshooting

Screen frequencies within ±2% (the crystal itself should be within ±0.01 %) and duty cycle within 35–65%. Also check that divider outputs track the measured CLK6M by ÷2, ÷4, ÷32 and ÷128 respectively. Use the scope to check voltage: 5 V logic low −0.3…0.45 V, high 4.0…5.3 V; Pi-facing logic low −0.3…0.45 V, high 2.7…3.6 V. A logic analyzer alone cannot establish safe output voltage.

Compare BCLK to PI_BCLK and LRCLK to PI_LRCLK with both scope channels: the paths should be non-inverting, with small propagation delay. At 50 MS/s, each sample is 20 ns; this is a gross polarity/timing check, not a precision jitter measurement.

5 · Digital data paths — test all four left/right combinations

Keep the standalone digital fixture; the crystal keeps the board clocked. No channel boards may be attached while their Q bus inputs are tied to rails. Every tie change requires the full off/rewire/on sequence from step 4.

Keep DIO1 on MCLK. Add DIO6 and scope 1+ to U6.4 (DIN), DIO7 to J4.12 (QL), DIO8 to J4.14 (QR), and DIO9 plus scope 2+ to J2.6 (PI_DIN). Both scope minus leads remain at GND. Input 0 means tie to board GND; input 1 means tie to board +5 V. Do not drive these 5 V HC inputs from 3.3 V AD3 DIO outputs.

MCLK low selects QR; MCLK high selects QL
QL / QR tiesDIN and PI_DIN expected
0 / 0Constant low
1 / 0Follow MCLK
0 / 1Inverse of MCLK
1 / 1Constant high

Judge the centre of each MCLK half-cycle, after propagation delay. DIN is 5 V logic; PI_DIN must remain 3.3 V logic, using the voltage limits in step 4. Record actual QL/QR states as well as outputs. Save each capture with its case name. After finishing, power off and remove all four-case test ties before adding either channel.

6 · Power + digital — make the digital board drive the pump
  1. Only continue after both standalone tests pass. Turn Korad and all AD3 outputs off and let the rails discharge. Remove the W1 wire from power J3.10. W1 is not used at all in this test; the digital board’s crystal-derived divider now drives PUMP.
  2. Join the power J3 and digital J4 buses with the same numbered pins aligned, using the intended connectors. For a minimal flywire fixture, connect J4.1 to J3.1 (GND), J4.2 to J3.2 (+5V), and J4.10 to J3.10 (PUMP). Check continuity and absence of shorts while unpowered. No other bus wires are needed for this two-board pump test.
  3. Use one Korad feed: red to digital J2.1, black to J2.2. Retain AD3 V+ to digital J2.3 at 3.30 V and J1 at 1–2; nothing on J2.7. Leave the absent QL/QR inputs tied low during this two-board-only test.
  4. Probe PUMP at power J3.10 with DIO10 and the negative rail at J3.16 with scope 2+. Scope 1+ measures J3.2. Start V+, then the Korad. Confirm 192 kHz reaches the power board and repeat the step 3 rail measurements, then references after powering off to move probes.
  5. Record supply current and voltages. This establishes that the digital divider can operate the pump. It does not prove loaded channel performance. Shut down the Korad and V+ before disconnecting.

There must be one driver on PUMP: AD3 W1 for the standalone power test, or the digital board for the combined test. Never connect both outputs to that net.

7 · Full stack, then the Raspberry Pi

Both channels are now fully populated, including their seven 100 nF decoupling capacitors. Before powering a channel, check all 20 required top-side pad connections on it against its assembly map; unplated holes do not join top and bottom copper automatically. Confirm J21: 1–2 on the left board, 2–3 on the right board.

The minimum before the Pi is the stack test, which adds the channel boards one at a time so a faulty one is caught alone: power + digital + left channel (input shorted) → rails at power J3 and the left modulator output QL at digital J4.12 against MCLK; add the right channel → rails again and QR at J4.14; then references, PI_BCLK/PI_LRCLK and PI_DIN/PI_BCLK at the Pi header. No Pi, +3.3 V still from AD3 V+. PI_DIN must toggle continuously at 3.3 V logic; a constant line means a stuck modulator, a wrong J21 or a dead bus line. Start the +5 V current limit at 0.30 A.

  1. Power off, remove the AD3 V+ wire from J2.3 and every probe. Connect the Pi's I²S GPIO header to J2 with matching pin numbers; the Pi now supplies +3.3 V to J2.3 and shares GND. Never leave AD3 V+ connected once the Pi is attached.
  2. Power the stack from the Korad first, then boot the Pi, and capture with the Pi's I²S receiver. Audio-quality measurements (SNR, THD, frequency response) happen there, not in these screens.
  3. If one channel misbehaves, run the detailed per-channel test (left or right): it uses DIO inputs and a 1 kHz tone from W1 and needs the stack reduced to power + digital + that channel.
# Browser front end (same tests, big buttons, resume support):
python assembly/bench/gui.py      # then open http://127.0.0.1:8090
# Terminal route. --probe declares each scope channel's probe: 10,1 = CH1 10x probe, CH2 1x probe (current BNC fixture)
python assembly/bench/run.py power --probe 10,1
python assembly/bench/run.py digital --ad3-3v3 --probe 10,1
python assembly/bench/run.py stack --ad3-3v3 --probe 10,1
# optional per-channel debugging:
python assembly/bench/run.py left --ad3-3v3 --probe 10,1

Follow the full fixture instructions in the SDK test README and the per-board “Board tests · AD3” stage below. A simulated PASS does not qualify a physical board.

Troubleshooting and what to record
ObservationNext check, with power off before moving connections
Korad in CC; voltage collapsesCheck shorts, IC orientation, reversed electrolytics, wrong bus alignment and a ground lead on −5V. Do not increase the current limit to bypass the symptom.
+5 V good, negative rail near 0 VVerify 192 kHz at J3.10; then U1 supply and enables, WL1, pump capacitor/diode orientation and solder joints. No negative rail is expected with the clock stopped.
“−5V” is positiveStop. Verify probe polarity and D1/D2 orientation against KiCad. Do not attach a channel.
Negative rail good, reference wrongCheck U2 orientation and supplies, reference resistor values and joints. Do not diagnose the negative reference until the negative rail is established.
No digital clocksScope J1.1 first. No 6.144 MHz there: check +5 V at U9.14, that U9 is a 74HCU04, the Y1/C16/C17/R10/R11 joints and that nothing loads J1.1. 6.144 MHz at J1.1 but nothing at U4.10: check the J1 shunt is across 1–2, U3 (74HCT132) and its links. Clock at U4.10 but no divider outputs: check U4.11 reset held low. A floating or wrong clock-select connection can look like a dead counter.
Oscillator runs far from 6.144 MHz (tens of MHz or a sub-harmonic)U9 is probably a buffered 74HC04 instead of the unbuffered 74HCU04, or R11 is not 2k2; see design notes §5. Do not test the divider on a wrong clock.
All digital frequencies wrong by the same factorCheck the crystal marking and the measured J1.1 frequency. CLK6M is 6.144 MHz; the bus MCLK is 1.536 MHz.
5 V clocks good, Pi outputs missingCheck the separate +3.3 V rail, U8 and the required bottom-only-board wire links.
Mux wrong or erraticVerify QL/QR are actually tied to the intended rails, U6 enable is low, MCLK reaches U6.1, and both channel boards are disconnected.
Clocks stop or rails sag when a script opensOnly one application owns the AD3; opening a script resets W1 and V+. With --ad3-3v3 the +3.3 V rail comes from V+ and is only enabled inside each powered step. The crystal clock itself needs only +5 V.
SDK cannot load or find AD3Close WaveForms, inspect python assembly/bench/run.py devices, and check the installer notes. Device enumeration alone does not exercise hardware outputs.

For each run record: board/revision, date, clock source and measured frequency, Korad current limit and measured current, rail means and ripple, clock frequencies/levels, mux case results and any heating or failed checks. Save WaveForms captures and the workspace separately; the assembly backup does not include WaveForms files. Do not mark skipped tests as passed.

Stop sequence: Korad off → W1 stop → AD3 V+ off → verify discharge. If software freezes or USB disconnects, turn the Korad off yourself; software cannot guarantee shutdown after a lost connection.

Guide checked against the current PCB snapshot (rev B digital board with the on-board Pierce oscillator) and existing provisional limits on 16 September 2026. No physical board measurements were made while updating it. References: KORAD KD-series manuals, KD-series manufacturer manual, RND-branded copy, AD3 electrical specifications, WaveForms Wavegen settings, local screening limits and validated probe plans.

Assembly checklist & KiCad reference Back to testing guide ↑

PCB reference

Selected Top connection · square = pin 1
Coordinates in mm, KiCad absolute origin. Copper fills and exact pad shapes omitted; verify in KiCad.